1. Field of the invention
The present invention relates generally to fiber optic data transmission systems, and more particularly to an apparatus for decoding a variable clock rate and for detecting and determining the duration of a data bit of an incoming digital signal occurring at a variable rate for use in a fiber optic work station capable of operation in a plurality of data rates without user or software intervention.
2. Description of the Prior Art
Fiber optics have been found to be particularly efficient for transmission of digital data between computer work stations. A present day work station configuration may employ multiple slave work stations, wherein advances in technology have permitted newly emplaced work stations to operate at a higher data rate than the earlier emplaced work stations. For example, while the older work stations may operate at a maximum of 307.2 Kbit/sec, a present day work station may operate at 1.8 Mbit/sec. A system for detecting the data rate (e.g., high speed bit rate or low speed bit rate) capability of the work station and adjusting the transmitted data rate automatically without software or operator intervention is described in U.S. patent application Ser. 121,389, Dynamic Speed Shifter for Fiber Optic Work Station, assigned to the assignee of the present invention, and which is hereby incorporated by reference.
As a consequence of the logic arrangement conventionally utilized by programmable array logic for asynchronous transmission of fiber optic data, using bi-phase zero data encoded in a self-clocking serial data transmission mode, the duration of each data bit and the embedded clock pulse may vary from pulse to pulse. In order to retransmit data to successive work stations, or back to the host computer, it is essential that the clock pulses and data bit duration be accurately reconstructed substantially in real time. Conventional decoding techniques which assume a 50 percent duty cycle in which the receiver attempts to sample at the center of each bit time, are inaccurate where the bi-phase pulse is asymmetrical and of varying duty cycle. Further, since bi-phase data may have transistions encoded within the data bit, as in a zero bit, the mere detection of a transition is insufficient to distinguish the start and end of a data bit.
The present invention improves over the prior art by providing an apparatus which detects the start and end transitions defining a bi-phase encoded data bit and distinguishes against transitions encoded within the data bit, and is useful for a dynamically varying bit rate and bit duration. It further provides, without additional circuitry, for receiving and decoding the embedded clock rate.